Various thin film layers for semiconductor devices may be deposited by chemical vapor deposition (CVD) and/or plasma-enhanced chemical vapor deposition (PECVD) processes. Some memory devices, such as NAND flash memory, are arranged in two-dimensional arrays. Because such memory devices are limited to a planar arrangement, die size and memory density parameters may constrain the total memory capacity of the device. In turn, moving to larger die sizes to expand memory capacity may comparatively increase the cost of the memory device, which may delay adoption of larger capacity memory devices. Certain approaches for arranging memory gates into three-dimensional (3D) arrays have been proposed. Some of these approaches incorporate transistors formed by patterning stacks of alternating film composition. FIG. 1 schematically shows an example film stack 1000 including alternating layers of first film 1020 and second film 1040 on a substrate 1060. These 3D arrays are sometimes utilized to form vertically integrated memory (VIM) structures.
Oftentimes, the unit layers used to form a VIM structure on a substrate have an as-deposited internal stress. In many cases the as-deposited internal stress is compressive. When many layers are positioned on top of one another, this internal stress may build up, thereby causing the coated substrate to bow instead of being flat. This bowing is undesirable because it can make subsequent processing more difficult. When the bow of a substrate exceeds a certain level, the substrate may be unusable.
In addition to internal stress, the roughness of a stack has an impact on the ability to conduct lithography reliably. If the surface of a stack is too rough, the incident radiation employed in photolithography will scatter too much. Also, the roughness of the stack is determined by the maximum roughness of any given layer in the stack. Therefore, it is important that each and every layer in the stack have a relatively low roughness.